<!doctype html><html lang=en><head><meta charset=utf-8><meta name=viewport content="width=device-width,initial-scale=1,viewport-fit=cover"><base href=https://www.lowrisc.org><link rel=icon type=image/png sizes=32x32 href=/favicon.png><title>RTL simulation &middot; lowRISC: Collaborative open silicon engineering</title><link href=/main.21c9d.css rel=stylesheet><script type=application/javascript>var doNotTrack=false;if(!doNotTrack){(function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){(i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)})(window,document,'script','https://www.google-analytics.com/analytics.js','ga');ga('create','UA-53520714-1','auto');ga('send','pageview');}</script></head><body><header><nav class="navbar navbar-expand-md navbar-light"><div class=container><a class=navbar-brand href=#><img src=/img/logo/logo-dualcolor.svg alt=lowRISC></a>
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<span class=navbar-toggler-icon></span></button><div class="collapse navbar-collapse" id=navbarCollapse><ul class="navbar-nav ml-auto"><li class=nav-item><a href=/our-work class=nav-link>Our work</a></li><li class=nav-item><a href=/open-silicon class=nav-link>Open Silicon</a></li><li class=nav-item><a href=/community class=nav-link>Community</a></li><li class=nav-item><a href=/blog class=nav-link>Blog</a></li><li class=nav-item><a href=/jobs class=nav-link>Jobs</a></li><li class=nav-item><a href=/about class=nav-link>About us</a></li><li class=nav-item><a class="btn lr-navbar-btn-gh" href=https://github.com/lowrisc>GitHub</a></li></ul></div></div></nav></header><main role=main><div class=container><h1>RTL simulation</h1><p>Here we describe how to simulate the lowRISC SoC using Verilator.</p><h3 id=compilation:514870219d3abfdff5b6e72bff95cfe8>Compilation</h3><p>To compile a simulator for the lowRISC SoC:</p><pre><code>cd $TOP/vsim
make sim
</code></pre><p>This generates a simulator named <code>DefaultConfig-sim</code>. It is optimized for
simulation speed and does not generate a waveform. If the compilation time is
too long on your machine, you can disable compiler optimization by commenting
out the optimization flags in <code>Makefile</code>:</p><pre><code># remove optimization if compilation takes too long or runs out of memory
veri_opt_flags = -O3 -CFLAGS &quot;-O1&quot;
</code></pre><p>If a waveform is needed for debugging failed test cases, a debugging simulator
can be compiled by</p><pre><code>cd $TOP/vsim
make sim-debug
</code></pre><p>The resulting simulator is named <code>DefaultConfig-sim-debug</code>.</p><h3 id=running-simulations:514870219d3abfdff5b6e72bff95cfe8>Running simulations</h3><p>The simulator recognizes the following arguments:</p><pre><code>+vcd                    enable waveform output.
+vcd_name=FILE_NAME     set the VCD file name, &quot;verilated.vcd&quot; in default.
+load=HEX_FILE          specify the hex file (memory image).
+max-cycles=NUM         specify the maximal number of simulation cycles.
</code></pre><p><a name=elf2hex></a>The <code>+vcd</code> and <code>+vcs_name</code> arguments are only effective with the debugging simulator. Executables must be translated to hex files (memory image) for simulation. <code>elf2hex</code> is a program provided by riscv-fesvr for this purpose.</p><pre><code># translate rv64ui-p-add to rv64ui-p-add.hex
elf2hex 16 4096 rv64ui-p-add &gt; rv64ui-p-add.hex
</code></pre><p>The second argument of <code>elf2hex</code>, 4096 in the above example, defines the size
of the memory image to be 64 KB. For large executables, modify this argument
accordingly.</p><p>To run a program without VCD:</p><pre><code>DefaultConfig-sim +max-cycles=100000000 +load=rv64ui-p-add.hex | spike-dasm &gt; rv64ui-p-add.log
</code></pre><p>where <code>rv64ui-p-add.log</code> has the instruction trace.</p><p>If a VCD is required:</p><pre><code>DefaultConfig-sim-debug +vcd +vcd_name=rv64ui-p-add.vcd +max-cycles=100000000 \
  +load=rv64ui-p-add.hex | spike-dasm &gt; rv64ui-p-add.log
</code></pre><p>Then the waveform is stored in <code>rv64ui-p-add.vcd</code>.</p><h3 id=running-the-isa-regression-test:514870219d3abfdff5b6e72bff95cfe8>Running the ISA regression test</h3><p>To run a regression test:</p><pre><code>cd $TOP/vsim
make -j$(nproc) run-asm-tests
</code></pre><p>If any test case ever failed, again using <code>rv64ui-p-add</code> as an example, a VCD for this test case can be generated:</p><pre><code>make output/rv64ui-p-add.verilator.vcd
</code></pre><h3 id=other-useful-makefile-targets:514870219d3abfdff5b6e72bff95cfe8>Other useful Makefile targets</h3><pre><code># generate Verilog for the Chisel Rocket-cores
make verilog
</code></pre></div></main><footer class=lr-footer><div class=container><div class=row><div class="col-lg-2 d-none d-lg-block"><img src=/img/logo/logo-dualcolor.svg width=150px></div><div class=col><p>The text content on this website is licensed under a <a href=https://creativecommons.org/licenses/by/4.0/>Creative Commons Attribution 4.0 International License</a>, except where otherwise noted. No license is granted for logos or other trademarks. Other content &copy; lowRISC Contributors.</p><a href=/privacy-policy>Privacy and cookies policy</a>
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